TSMC Completes Design Infrastructure for Its 5nm Process Enabling Next Generation SoC Designs

TSMC has announced the completion and delivery of its 5nm design infrastructure within the Open Innovation Platform (OIP). This full release enables 5nm systems-on-chip (soC) designs for next generation mobile and high-performance computing (HPC) applications.

The company's 5nm process is already in risk production and offers IC designers a new level of performance and power optimization.

Compared with TSMC’s 7nm process, its innovative scaling features deliver 1.8X logic density and 15% speed gain on an ARM Cortex-A72 core, along with superior SRAM and analog area reduction enabled by the process architecture. The 5nm process enjoys the benefits of process simplification provided by EUV lithography, and is making excellent progress in yield learning, achieving the best technology maturity at the same corresponding stage as compared to TSMC's previous nodes.


TMSC says customers have already started intensive design engagements, paving the way for product tape-outs, pilot activities and early sampling. Apple uses the company's 7nm process to manufacture its A12 processors and is likely to use the new 5nm process for future chip designs.

“TSMC’s 5-nanometer technology offers our customers the industry’s most advanced logic process to address the exponentially growing demand for computing power driven by AI and 5G,” said Cliff Hou, Vice President of Research & Development/Technology Development at TSMC. “5-nanometer technology requires deeper design-technology co-optimization. Therefore, we collaborate seamlessly with our ecosystem partners to ensure we deliver silicon-validated IP blocks and EDA tools ready for customer use. As always, we are committed to helping customers achieve first-time silicon success and faster time-to-market.”

The entire TSMC 5nm design infrastructure is available now from TSMC Online for customer downloads.