TSMC debuted new A16 Technology at the company's 2024 North America Technology Symposium yesterday. TSMC is the sole manufacturer of Apple Silicon, so it's likely that we'll see this technology used in future chips from Apple.
The A16 1.6nm process features leading nanosheet transistors with a backside power rail solution, bringing greatly improved logic density and performance. TSMC expects to begin production of chips using the A16 process in late 2016.
With TSMC's industry-leading N3E technology now in production, and N2 on track for production in the second half of 2025, TSMC debuted A16, the next technology on its roadmap. A16 will combine TSMC's Super Power Rail architecture with its nanosheet transistors for planned production in 2026. It improves logic density and performance by dedicating front-side routing resources to signals, making A16 ideal for HPC products with complex signal routes and dense power delivery networks. Compared to TSMC's N2P process, A16 will provide 8-10% speed improvement at the same Vdd (positive power supply voltage), 15-20% power reduction at the same speed, and up to 1.10X chip density improvement for data center products.
Notably, TSMC also announced that its upcoming N2 technology will come with NanoFlex, a breakthrough in design-technology co-optimization.
TSMC NanoFlex provides designers with flexibility in N2 standard cells, the basic building blocks of chip design, with short cells emphasizing small area and greater power efficiency, and tall cells maximizing performance. Customers are able to optimize the combination of short and tall cells within the same design block, tuning their designs to reach the optimal power, performance, and area tradeoffs for their application.
The company unveiled several other advancements at the symposium, including System-on-Wafer (TSMC-SoW) technology to address future AI requirements for hyperscaler datacenters. More details in the full announcement linked below...
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The A16 1.6nm process features leading nanosheet transistors with a backside power rail solution, bringing greatly improved logic density and performance. TSMC expects to begin production of chips using the A16 process in late 2016.
With TSMC's industry-leading N3E technology now in production, and N2 on track for production in the second half of 2025, TSMC debuted A16, the next technology on its roadmap. A16 will combine TSMC's Super Power Rail architecture with its nanosheet transistors for planned production in 2026. It improves logic density and performance by dedicating front-side routing resources to signals, making A16 ideal for HPC products with complex signal routes and dense power delivery networks. Compared to TSMC's N2P process, A16 will provide 8-10% speed improvement at the same Vdd (positive power supply voltage), 15-20% power reduction at the same speed, and up to 1.10X chip density improvement for data center products.
Notably, TSMC also announced that its upcoming N2 technology will come with NanoFlex, a breakthrough in design-technology co-optimization.
TSMC NanoFlex provides designers with flexibility in N2 standard cells, the basic building blocks of chip design, with short cells emphasizing small area and greater power efficiency, and tall cells maximizing performance. Customers are able to optimize the combination of short and tall cells within the same design block, tuning their designs to reach the optimal power, performance, and area tradeoffs for their application.
The company unveiled several other advancements at the symposium, including System-on-Wafer (TSMC-SoW) technology to address future AI requirements for hyperscaler datacenters. More details in the full announcement linked below...
Read More